| _BGP_IP_Addr_t | |
| _BGP_Personality_DDR_t | |
| _BGP_Personality_Ethernet_t | |
| _BGP_Personality_Kernel_t | |
| _BGP_Personality_Networks_t | |
| _BGP_PersonalityTreeInfo_t | |
| _cheader_data | |
| _Kernel_Coordinates | Converts all ranks into a XYZT Coordinate |
| CCMI::Executor::AllreduceState::_phase_state | |
| CCMI::Executor::AllreduceBase | |
| CCMI::Executor::AllreduceState | Allreduce (and Reduce) persistent state data This class allocates storage for receive buffers and schedule data |
| BGP_UPC_Read_Counter_Config_Struct | |
| BGP_UPC_Read_Counters_Struct | |
| CCMI::Schedule::BinomialTreeSchedule | |
| CCMI_Callback_t | |
| CCMI::MultiSend::CCMI_Multicast_t | |
| CCMI::MultiSend::CCMI_MulticastRecv_t | |
| CCMIQuad | |
| CCMI::ConnectionManager::ConnectionManager | A class to manage multisend connections for collective protocols |
| DCMF_Allreduce_Configuration_t | Allreduce configuration |
| DCMF_Alltoallv_Configuration_t | Alltoallv configuration |
| DCMF_Barrier_Configuration_t | Barrier configuration |
| DCMF_Broadcast_Configuration_t | Broadcast configuration |
| DCMF_Callback_t | Completion callback information descriptor |
| DCMF_Configure_t | The object used to pass around API Configuration info |
| DCMF_Control_Configuration_t | Control Protocol Configuration Information |
| DCMF_Error_t | DCMF Error callback results |
| DCMF_Get_Configuration_t | Point-to-point get configuration |
| DCMF_Hardware_t | Hardware information data type |
| DCMF_Manytomany_Configuration_t | Many to many configuration |
| DCMF_Messager_advance_options | |
| DCMF_Multicast_Configuration_t | Multicast configuration. The connection ids here go from 0 - (nconnections-1) |
| DCMF_Multicast_t | A structure to pass parameters for the multisend multicast operation |
| DCMF_MulticastRecv_t | A structure to pass parameters for the multisend multicast post recv operation |
| DCMF_NetworkCoord_t | A structure to describe a network coordinate |
| DCMF_Put_Configuration_t | 1-sided point-to-point put configuration |
| DCMF_Reduce_Configuration_t | Reduce configuration |
| DCMF_Send_Configuration_t | Point-to-point send configuration |
| DCQuad | Common quad datatype (4 words, 16 bytes) |
| DCR_GlobalInt_t | Global Interupt DCR. Note that userEnables returns the uptree state in diagnostic read mode |
| DMA_AddressingAppSegment_t | __INLINE__ definition |
| DMA_AddressingAppSegmentSet_t | Application Segment Set |
| DMA_AddressingGlobalAppSegmentSetInfo_t | Global Application Segment Set Info |
| DMA_AddressingInitSharedMemoryHeader | Shared Memory Header |
| DMA_AddressingLocalAppSegmentSetInfo_t | Local Application Segment Set Info |
| DMA_Counter_t | Software DMA Counter Structure |
| DMA_CounterAppSegment_t | Counter Application Segment |
| DMA_CounterGroup_t | DMA Counter Group Structure |
| DMA_CounterHw_t | Hardware DMA Counter |
| DMA_CounterStatus_t | DMA Counter Hardware Status structure |
| DMA_Fifo_t | Software DMA Fifo structure |
| DMA_FifoHW_t | Hardware DMA Fifo |
| DMA_InjDescriptor_t | DMA Injection Descriptor Structure |
| DMA_InjFifo_t | Injection DMA Fifo Structure |
| DMA_InjFifoGroup_t | DMA Injection Fifo Group Structure |
| DMA_InjFifoRgetFifoFullHandlerEntry_t | Remote Get Fifo Full Handler Table Entry |
| DMA_InjFifoStatus_t | DMA Injection Fifo Status structure |
| DMA_PacketHeader_t | Torus DMA Hardware Packet Header |
| DMA_PersonalityInfo_t | Static Info from Personality |
| DMA_RecFifo_t | Reception DMA Fifo Structure |
| DMA_RecFifoGroup_t | DMA Reception Fifo Group Structure |
| DMA_RecFifoMap_t | DMA Reception Fifo Map Structure |
| DMA_RecFifoSharedMemory_t | DMA Reception Fifo Shared Memory Structure |
| DMA_RecFifoStatus_t | DMA Reception Fifo Status Structure |
| CCMI::Executor::Executor | Base Class for all Executors |
| fp32_fp32_t | MAXLOC and MINLOC operation element type for float (32-bit) and float (32-bit) data |
| fp32_int32_t | MAXLOC and MINLOC operation element type for float (32-bit) and signed 32-bit data |
| fp64_fp64_t | MAXLOC and MINLOC operation element type for double (64-bit) and double (64-bit) data |
| fp64_int32_t | MAXLOC and MINLOC operation element type for double (64-bit) and signed 32-bit data |
| GlobInt_Status_t | Information returned by status reads. Note that userEnables returns the uptree state in diagnostic read mode |
| int16_int32_t | MAXLOC and MINLOC operation element type for signed 16-bit and signed 32-bit data |
| int32_int32_t | MAXLOC and MINLOC operation element type for signed 32-bit and signed 32-bit data |
| LockBox_Barrier_t | Structure contains information required to perform a lockbox barrier. This structure will be filled out by the LockBox_AllocateBarrier() function |
| CCMI::Logging::LogMgr | |
| CCMI::MultiSend::ManytomanyInterface | Message passing interface suitable for alltoall communiction |
| CCMI::Mapping | |
| CCMI::MultiSend::MulticastInterface | Message passing interface suitable for broadcasts, barriers and reductions |
| CCMI::Executor::RecvCallbackData_t | Client data for multisend receive done callback |
| CCMI::Schedule::Schedule | |
| CCMI::Executor::SendCallbackData_t | Client data for multisend send done callback |
| CCMI::Executor::AllreduceBase::SendState | |
| SPR_ccr0_t | CCR0: Core Configuration Register 0 |
| SPR_csrr0_t | CSRR0 is an SPR that is used to save machine state on critical interrupts |
| SPR_csrr1_t | CSRR1 CSRR1 is an SPR that is used to save machine state on critical interrupts |
| SPR_dac1_t | DAC1: One of two Data Address Compare registers that specifieds the address upon which DAC (and/or DVC) debug events should occur |
| SPR_dac2_t | DAC2: One of two Data Address Compare registers that specifieds the address upon which DAC (and/or DVC) debug events should occur |
| SPR_dbcr0_t | DBCR0 is an SPR that is used to enable debug modes and events, reset the processor, and control timer operation when debugging |
| SPR_dbcr1_t | DBCR1 is an SPR that is used to configure IAC debug events |
| SPR_dbcr2_t | DBCR2 is an SPR that is used to configure DAC and DVC debug events |
| SPR_dbsr_t | DBSR: The Debug Status Register contains status on debug events as well as information on the type of the most recent reset |
| SPR_dear_t | DEAR contains the address that was referenced by a load, store, or cache management instruction that caused an Alignment, Data TLB Miss, or Data Storage exception |
| SPR_dec_t | DEC: The Decrementer is a 32-bit privileged SPR that decrements at the same rate that the time base increments |
| SPR_iac2_t | IAC2: One of four IAC registers used to specify the addresses upon which IAC debug events should occur |
| SPR_iac3_t | IAC3: One of four IAC registers used to specify the addresses upon which IAC debug events should occur |
| SPR_iac4_t | IAC4: One of four IAC registers used to specify the addresses upon which IAC debug events should occur |
| SPR_iacIAC1t | IAC1: One of four IAC registers used to specify the addresses upon which IAC debug events should occur |
| SPR_icdbdr_t | ICDBDR: Instruction Cache Debug Data Register |
| SPR_icdbtrh_t | ICDBTRH: Instruction Cache Debug Tag Register High |
| SPR_icdbtrl_t | ICDBTRL: Instruction Cache Debug Tag Register Low |
| SPR_ivor0_t | IVOR0 - Critical Interrupt Vector Offset |
| SPR_ivor10_t | IVOR10 - Decrementer Interrupt Vector Offset |
| SPR_ivor11_t | IVOR11 - Fixed Interval Timer Interrupt Vector Offset |
| SPR_ivor12_t | IVOR12 - Watchdog Timer Interrupt Vector Offset |
| SPR_ivor13_t | IVOR13 - Data TLB Error Interrupt Vector Offset |
| SPR_ivor14_t | IVOR14 - Instruction TLB Error Interrupt Vector Offset |
| SPR_ivor15_t | IVOR015 - Debug Interrupt Vector Offset |
| SPR_ivor1_t | IVOR1 - Machine Check Interrupt Vector Offset |
| SPR_ivor2_t | IVOR2 - Data Storage Interrupt Vector Offset |
| SPR_ivor3_t | IVOR3 - Instruction Storage Interrupt Vector Offset |
| SPR_ivor4_t | IVOR4 - External Input Interrrupt Vector Offset |
| SPR_ivor5_t | IVOR5 - Alignment Interrupt Vector Offset |
| SPR_ivor6_t | IVOR6 - Program Interrupt Vector Offset |
| SPR_ivor7_t | IVOR7 - Floating Point Unavailable Interrupt Vector Offset |
| SPR_ivor8_t | IVOR8 - System Call Interrupt Vector Offset |
| SPR_ivor9_t | IVOR9 - Auxiliary Processor Unavailable Interrupt Vector Offset |
| SPR_ivpr_t | IVPR - provides the high-order 16 bits of the effective address of the interrupt vectors, for all interrupt types |
| SPR_mcsr_t | MCSR: The Machine Check Status Register contains status to allow the Machine Check interrupt handler software to determine the cause of a machine check exception |
| SPR_mcsrr0_t | MCSRR0 is an SPR that is used to save machine state on Machine Check interrupts |
| SPR_mcsrr1_t | MCSRR1 is an SPR that is used to save machine state on Machine Check interrupts |
| SPR_mmucr_t | MMUCR: Memory Management Unit Control Register |
| SPR_msr_t | MSR: Controls important chip functions such as enabling/disabling of interrupts |
| SPR_sprg0_sprg7_t | SPRG0-SPRG7: Special Purpose Registers 0 through 7. Provided for general purpose system-dependent software use |
| SPR_srr0_t | SRR0 is an SPR that is used to save machine state on non-critical interrupts |
| SPR_srr1_t | SRR1 is an SPR that is used to save machine state on non-critical interrupts |
| SPR_tcr_t | TCR: The Timer Control Register is a privileged SPR that controls DEC, FIT, and Watchdog Timer operation |
| SPR_tsr_t | TSR: The Timer Status Register is a privileged SPR that records the status of DEC, FIT, and Watchdog Timer events |
| T_BGP_Pers_L1Cfg | |
| T_BGP_Pers_L3Cfg | |
| T_BGP_Pers_L3Select | |
| T_BGP_Personality_t | |
| T_BGP_QuadWord | |
| T_BGP_RAS_Detail | |
| T_BGP_RAS_Event | |
| T_BGP_SprgDataI | |
| T_BGP_SprgDST2 | |
| T_BGP_SprgShMem | |
| T_BGP_SprgTextI | |
| T_BGP_TLB_Data | |
| T_BGP_TLB_Entry | |
| T_BGP_TLB_Word0 | |
| T_BGP_TLB_Word1 | |
| T_BGP_TLB_Word2 | |
| T_BGP_VMM_RasData | |
| T_BGP_VMM_State | |
| T_BGP_VMM_TLB_Swap | |
| uint16_int32_t | MAXLOC and MINLOC operation element type for unsigned 16-bit and signed 32-bit data |
| uint32_int32_t | MAXLOC and MINLOC operation element type for unsigned 32-bit and signed 32-bit data |
| uint32_uint32_t | MAXLOC and MINLOC operation element type for unsigned 32-bit and unsigned 32-bit data |
| uint64_int32_t | MAXLOC and MINLOC operation element type for unsigned 64-bit and signed 32-bit data |
| uint64_uint64_t | MAXLOC and MINLOC operation element type for unsigned 64-bit and unsigned 64-bit data |
